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MU9C8358L Quad 10/100Mb Ethernet Filter Interface
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* * * * * * * 10/100Mb Ethernet switching, bridging, and remote access at wire speed Glueless connection to MUSIC LANCAM and most 10/100Mb Ethernet chip sets Offloads all DA/SA processing and management functions from host processor Scalable up to eight ports of 100Mb Ethernet sharing a common LANCAM database Support station lists from 0.25K up to 32K Full support of Unicast, Multicast, and Broadcast frames Built-in generic Processor port
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Four industry-standard 10/100Mb MII ports Supports station list up to 32K addresses Built-in arbitration supports eight 100Mb Ethernet ports Port ID identification and MAC Frame Reject signal based on DA search results Read search results from the Result port or CPU port Hardware support for Tag switching Optional automatic learning of new SAs Optional automatic Aging and Purging 208-pin LQFP package 3.3 Volt operation

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The MU9C8358L, when configured with MUSIC Semiconductors MU9Cx480B family of LANCAMs, provides a high performance, large capacity Ethernet address processing subsystem for use in Ethernet bridge, switch, or remote access products. The device is designed to work in multi-port systems that require a common address database for all ports. Built-in arbitration allows two MU9C8358L devices to share a common CAM database, supporting up to eight 100Mb/s Ethernet ports at wire speed.
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Because of the flexibility of the MU9C8358L, the best way to approach the feature set of the device is to first look at a typical Multiport 10/100Mb Ethernet application. The MU9C8358L captures the Destination address (DA) and the Source address (SA) of an incoming Ethernet frame on the MII port. After checking for a frame error or collision, the DA is processed and the result (associated data, usually a port ID) is made available. The SA then is checked, and either learned if new, or aged if already in the list. When the DA is processed, the MU9C8358L first checks if the frame is Unicast, Multicast, or Broadcast. Unicast frames destined for the same collision domain (visible on the same switch port as it came in on) are rejected. Unicast frames that are destined for a different collision domain (visible on a different switch port) are processed by the system. If the DA is found in the CAM database, the port ID associated with it is stored in the Result register. Multicast and Broadcast frames are not processed by the system. Instead they are identified and their classification is stored in the Result register. Once processing completes, the Result register is accessed through the Result port or Processor port. Provided the frame length is correct, and no errors are detected, the SA is processed. If the SA exists in the CAM database, the time stamp and Port ID are updated. If the SA is not found in the CAM database, the address is learned automatically, along with its Port ID and the current time stamp information. The built-in arbitration allows all ports equal access to the CAM database. The arbitration scheme gives DA processing the highest-priority, then SA processing. Address processing always has priority over management routines, such as purging aged entries, inserting permanent entries, deleting entries, or reading from the CAM database. Using the 70 ns speed grade CAMs and a 50 MHz system clock, there is sufficient time to support eight DA searches, eight SA searches, and one management routine, within the minimum frame time (about 6.2S). In addition, the arbitration bus allows the MU9C8358L to be used with future MUSIC devices, sharing a common CAM database.
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The MU9C8358L plays an integral role in the example of an Ethernet switching system, shown in Figure 2. This system can handle up to 32,768 addresses distributed over eight independent, bidirectional 100Mb Ethernet ports by utilizing two MU9C8358L devices and four LANCAMs connected as shown in Figure 1. The system is based on several industry-standard and proprietary busses, which are described in more detail later. The MII bus is "tapped" to collect packet data as it passes from the PHY to the MAC. That data is processed automatically by the MU9C8358L/LANCAM combination. The LANCAM bus is utilized to transfer the DA and SA to the CAMs for comparisons, and to transfer the match results from the CAMs to the MU9C8358L. The results of MU9C8358L/LANCAM data processing are available through the Result bus or through the Processor bus. In addition to the Result bus, there is a serial Tag port per MII port to relay the Tag ID to the system for systems that support Tag switching. The Arbitration bus provides communication between two MU9C8358L devices to service eight MII ports with a shared CAM-based station list.
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Figure 2: MU9C8358L Typical Application
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All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash ("/") are active LOW. Inputs should never be left floating. Pins designated as "Reserved" must not be connected to any external circuitry. Refer to the Electrical Characteristics section for more information.
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5;'>@B $' 5H.HLYH 'DWD ,QSXW 77/ RXD[3:0] is the 4-bit MII Receive Data nibble (see Timing Diagrams: Timing Data for RXD, RX_DV, and RX_ER). 5;B'9B $' 5H.HLYH 'DWD 9DOLG ,QSXW 77/ Data Valid is on RX_DV; RX_DV is asserted by the PHY at the beginning of the first nibble of the data frame and deasserted at the end of the last nibble of the frame. It indicates that the data is synchronous to RX_CLK and is itself synchronous to the clock (see Timing Diagrams: Timing Data for RXD, RX_DV, and RX_ER). 5;B(5B $' 5H.HLYH (UURU ,QSXW 77/ RX_ER indicates a data symbol error in 100Mb/s mode or any other error that the PHY can detect, even if the MAC is not capable of detecting that error (see Timing Diagrams: Timing Data for RXD, RX_DV, and RX_ER). 5;B&/.B $' 5H.HLYH &OR.N ,QSXW 77/ RX_CLK is the receive clock recovered from the data by the PHY. It is equal to 25 MHz in 100Base-X mode or 2.5 MHz in 10Base-X mode. &56B $' &DUULHU 6HQVH ,QSXW 77/ Carrier sense CRS indicates that the medium is active (non-idle) and remains asserted during a collision. For Rx or Tx: CRS is HIGH in 10/100Base-X half-duplex mode; for Rx it is HIGH in repeater, full-duplex, and loopback modes. CRS is not synchronized to RX_CLK. &2/B $' &ROOLVLRQ ,QSXW 77/ Collision detect COL is asserted by the PHY upon detection of a collision on the medium and remains asserted as long as the collision persists. It is HIGH in half-duplex modes and remains HIGH for 1 microsecond following the end of transmission; it is LOW in full-duplex mode. It is asserted in response to signal_quality_error message from the PMA in 10Base-X Heartbeat mode.
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5(-B $' 5HMH.W 2XWSXW 77/ REJ is the reject packet command issued by the MU9C8358L; the minimum length is 110 nanoseconds. REJ is driven HIGH to reject a data frame, and can be detected by and responded to by the MAC devices from 2 bit times after SFD to 512 bit times (64 byte times) after SFD. The REJ signal can be made active LOW by setting Bit 0 in the SSCFG register. (See Timing Diagrams: Timing Data for REJ (Base 100.)) )5;B(5B $' )UDPH (UURU 2XWSXW 77/ The Forced Receive Error pins provide the logical OR of the RX_ER and REJ lines for the appropriate MII port (see Timing Diagrams: Timing Data for FRX_ER in Relation to REJ and RX_ER). 73B6'B $' 7DJ 3RUW 'DWD 2XWSXW 77/ The Tag Port Serial Data pin carries the destination Port ID to external circuitry as soon as it is collected from the CAM (see Timing Diagrams: Timing Data for Tag Ports TP_DV and TP_SD). 73B'9B $' 7DJ 3RUW 'DWD 9DOLG 2XWSXW 77/ The Tag Port Data Valid pins are driven HIGH for as long as unread data exists for each Destination Port ID. Pins TP_SD_A through TP_SD_D carry the Destination Port ID (4 bits) to external circuitry as soon as it is collected from the CAM (see Timing Diagrams: Timing Data for Tag Ports TP_DV and TP_SD).
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See Timing Diagrams: Timing Data for Result Port Interface and Table 1 for the Result Port bit descriptions.
Note: Although the result data register also can be read through the processor port, it is important to note that the means of retrieving the data must be unique. Therefore, if the user is not using the Result Port Interface, but is reading result data through the processor port, RP_NXT and RP_SEL should be pulled low. This ensures that all result data remains in the Result Data register until read through the processor port. RP_NXT and RP_SEL should be pulled low to 0 volts through a pull-down resistor (typically 10k ohms).
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See Timing Diagrams: Timing Data for Control Interfaces. 6<6&/. 6\VWHP &OR.N ,QSXW 77/ SYSCLK is the user-supplied system clock for synchronous chip operation. Optimum results are achieved when the SYSCLK is 50 MHz, although it may run slower with fewer than 8 ports and with an increased allowance for latency. The duty cycle must be between 45 to 55 percent. 5(6(7 5HVHW ,QSXW 77/ When system Reset is taken LOW, all internal state-machines are reset to their initial state and any data is cleared. All registers are returned to default values. /RESET is synchronous and should be held LOW for a minimum of two SYSCLK cycles. The user must set the LANCAM Segment Control register after asserting /RESET.
,1&5 ,Q.UHPHQW 7LPH 6WDPS &RXQWHUV ,QSXW 77/ INCR is a user command to invoke the built-in purge routine. Both STCURR and STPURG 8-bit counters are advanced one count on the rising edge of INCR, and the time stamp stored with each LANCAM entry is compared with STPURG. Matching entries subsequently are purged or deleted. This pin must be configured, if it is required, by setting bit 2 and bit 3 in the System Target (STARG) register. Each counter can be incremented individually through the Processor Port. (see Operational Characteristics: STARG System Target Register Mapping).
53>@ 5HVXOW 3RUW 'DWD 2XWSXW 7ULVWDWH 77/ The Result Port Data carries the results of recently processed packets detected on the MII ports. See Table 1 for details of the Result Port Data bit descriptions. These are identical to the Result Data register bits. 53B'9 5HVXOW 3RUW 'DWD 9DOLG 2XWSXW 77/ The Result Port Data Valid indicates that the RP port carries valid packet data. As long as there is valid packet data, RP_DV will stay HIGH. 53B1;7 5HVXOW 3RUW 1H[W 'DWD ,QSXW 77/ The Result Port Next pin brings the next result to the RP bus if RP_SEL is asserted. If there are no additional results available, the RP_DV will drop LOW after the time interval specified in the Result Port Timing specification. 53B6(/ 5HVXOW 3RUW 6HOH.W ,QSXW 77/ The Result Port Select pin controls RP[15:0] and RP_NXT. RP_NXT and RP_SEL are connected by a logical AND. Therefore, RP_SEL must be HIGH in order for RP_NXT to bring the next result to the RP bus. RP and RP_NXT from two MU9C8358L components (eight ports) can be wired together on a common bus in order to run these components in cascade. Refer to Figure 7 on page 21. RP_SEL can stay continuously HIGH if one MU9C8358L is being implemented. As long as there is valid packet data, RP_DV will stay HIGH.
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08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H ,175 3UR.HVVRU ,QWHUUXSW 2XWSXW 77/ /INTR goes LOW to signal that one of the four configurable interrupt conditions have been satisfied. The four separate conditions are configured by setting bits in the appropriate register. /INTR returns HIGH when the appropriate register is read. See Table 2 for details of which interrupt conditions are possible and which register must be read to reset the /INTR pin to HIGH. 7DEOH ,175 6HWWLQJV
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The Host Processor interface is asynchronous to the System Clock. This interface is controlled by the /PCS or /PCSS (whichever is appropriate) and PROC_RDY signals, which form the handshaking between the processor and the MU9C8358L. This allows the end system to use a processor that runs at a different clock speed than the clock required by the MU9C8358L. See Timing Diagrams: Timing Data for Host Processor Interface. 3&6 3UR.HVVRU 3RUW &KLS 6HOH.W ,QSXW 77/ Processor Chip Select is taken LOW by the host processor to gain access to the MU9C8358L Port or Chip registers. When two MU9C8358L devices are connected together, each device should have its own independent /PCS signal. 3&66 3UR.HVVRU 3RUW &KLS 6HOH.W 6\VWHP ,QSXW 77/ Processor Chip Select System is taken LOW by the host processor to gain access to the MU9C8358L System registers or to access the LANCAM. When two MU9C8358L devices are connected together, the /PCSS inputs should be connected together. :5,7( 3UR.HVVRU 3RUW 5HDG:ULWH ,QSXW 77/ Read/Write determines the direction of data flow into or out of the MU9C8358L host processor interface. If /WRITE is LOW, the data is written into the register selected by A[7:0] and /PCS or /PCSS; if HIGH, the data is read from the register selected by A[7:0] and /PCS or /PCSS. $>@ 3UR.HVVRU 3RUW $GGUHVV ,QSXW 77/ Processor Address bus A[7:0] selects the MU9C8358L register accessed by the host processor. '>@ 3UR.HVVRU 3RUW 'DWD ,QSXW2XWSXW 7ULVWDWH 77/ Processor Data bus D[15:0] is the tri-state processor data bus for the MU9C8358L. 352&B5'< 3UR.HVVRU 3RUW 5HDG\ 2XWSXW 7ULVWDWH 77/ When reading from or writing to any MU9C8358L internal register, the PROC_RDY tri-state output goes LOW on the falling edge of /PCS or /PCSS. It goes HIGH on the rising edge of the first SYSCLK after /PCS or /PCSS is LOW, to indicate that data is available (read) or data has been accepted (write).
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1. 2. RSTAT-/INTR only returns HIGH when all possible result data has been read. SSTAT-/INTR only returns HIGH when the LANCAM has become not full. Therefore, after the SSTAT register read has confirmed the status of the interrupt condition, an entry should be removed from the LANCAM by using the PURGE sequence.
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See Timing Diagrams: Timing Data for LANCAM Interface. '4>@ /$1&$0 %XV ,QSXW2XWSXW 7ULVWDWH 77/ DQ[15:0] tri-state 16-bit bus transfers data or instructions between the MU9C8358L and the LANCAM. When no data or instructions are present on the bus, the bus goes HIGH-Z. These pins have 50-k internal pull-up resistors. ( /$1&$0 %XV (QDEOH 2XWSXW 7ULVWDWH 77/ The /E chip enable is taken LOW to initiate LANCAM activity. On LANCAM read cycles, /E is taken HIGH after the MU9C8358L registers the data. This pin has a 50-k internal pull-up resistor. : /$1&$0 %XV :ULWH 2XWSXW 7ULVWDWH 77/ The MU9C8358L outputs /W (read/write select) to control the direction of data flow between the MU9C8358L and the LANCAM. If /W is LOW at the falling edge of /E, the MU9C8358L outputs data on the DQ[15:0] bus for the LANCAM as input. When /W is HIGH at the falling edge of /E, the LANCAM outputs data on the DQ[15:0] bus to the MU9C8358L as input.
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08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H &0 /$1&$0 %XV &RPPDQG 0RGH 2XWSXW 7ULVWDWH 77/ The MU9C8358L outputs /CM Data/Command Select to control whether the LANCAM interprets the DQ[15:0] bus contents as command information or data. If both /CM and /W are LOW at the falling edge of /E, the MU9C8358L outputs an instruction for the LANCAM to execute or a value for one of the LANCAM configuration registers. If /CM is LOW while /W is HIGH, then the LANCAM will output data from one of its configuration registers to the MU9C8358L. If /CM is HIGH while /W is LOW, the MU9C8358L will output data for the LANCAM to place in one of its data registers or memory. If /CM is HIGH while /W is HIGH, the LANCAM outputs data from one of its data registers or memory to the MU9C8358L. (& /$1&$0 %XV (QDEOH &KDLQ 2XWSXW 7ULVWDWH 77/ The Daisy Chain Enable signal performs two functions. The /EC signal enables the LANCAMs /MF output to show the results of a comparison. If /EC is LOW at the falling edge of /E in a cycle, the /MF flag output is enabled; otherwise, /MF is held HIGH. The /EC signal also enables the /MF-/MI daisy chain that serves to select the device with the highest-priority match in a string of LANCAMs. 0, /$1&$0 %XV 0DW.K )ODJ ,QSXW 77/ The /MI LANCAM Match flag input is used to indicate to the MU9C8358L the conditions of the LANCAM Match flag. The /MF output from the LANCAM should be connected to this pin. If more than one LANCAM is used, /MI should be connected to the /MF pin of the last LANCAM in the daisy chain. ), /$1&$0 %XV )XOO )ODJ ,QSXW 77/ The /FI LANCAM Full flag input is used to indicate to the MU9C8358L the condition of the LANCAM Full flag. The /FF output from the LANCAM should be connected to this pin. If more than one LANCAM is used, /FI should be connected to the /FF of the last device in the daisy chain. 5(6(7B/& 5HVHW /$1&$0 2XWSXW 77/ 6ODYH ,QVWDQ.H 1R &RQQH.WLRQ /RESET_LC is LOW whenever /RESET is LOW. It is taken HIGH only by writing to bit 0 in the System Dynamic Configuration (SDCFG) register. See SDCFG register information. /RESET_LC is used only on the master device; it is left unconnected on the slave device when two MU9C8358Ls are connected together.
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6<1& ,QSXW2XWSXW 77/ The MU9C8358L configured as MASTER provides this signal as an output. An MU9C8358L configured as a SLAVE uses this signal as input. This signal is not used in a single MU9C8358L application and may be left unconnected. This pin has a 50-k internal pull-up resistor. See Timing Diagrams: Timing Data for Control Interfaces. $5%>@ $UELWHU 3RUW ,QSXW2XWSXW 77/ The MU9C8358L configured as MASTER must monitor the attached slave device to determine which device gains access to the CAM in a given processing cycle. These signals are not used in a single MU9C8358L application, and may be left unconnected. These pins have 50-k internal pull-up resistors. See Timing Diagrams: Timing Data for Control Interfaces.
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Please refer to IEEE Standard 1149.1 for information on using the mandatory JTAG functions. The optional HIGH-Z function is implemented and may be activated by writing 0011 to the JTAG Instruction register. 7567 -7$* 5HVHW ,QSXW The /TRST is the Test Reset pin. It is internally pulled up with a 50-k resistor. It must be tied to /RESET or tied LOW when the JTAG port is not used. 7&. -7$* 7HVW &OR.N ,QSXW The TCK input is the Test Clock input. It can be tied at a valid logic level 1 when not in use. This pin is internally pulled up with a 50-k resistor. 706 -7$* 7HVW 0RGH 6HOH.W ,QSXW The TMS input is the Test Mode Select input. This pin is internally pulled up with a 50-k resistor. 7', -7$* 7HVW 'DWD ,QSXW ,QSXW The TDI input is the Test Data input. This pin is internally pulled up with a 50-k resistor. 7'2 -7$* 7HVW 'DWD 2XWSXW 2XWSXW The TDO output is the Test Data output. 7(67(1 This pin is used for internal MUSIC Semiconductor testing only. This pin has a 50-k pull-up resistor to VDD and may be left as "NO CONNECT" in system applications.
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9'' *1' 3RVLWLYH 3RZHU 6XSSO\ *URXQG These pins are the power supply connections to the MU9C8358L. VDD must meet the voltage supply requirements in the Operating Conditions section relative to the GND pins, which are at 0 Volts (system reference potential), for correct operation of the device. 5HY
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MU9C8358L internal functions are shown in Figure 4. Before discussing the individual blocks, the underlying principles are presented. The network interfaces are monitored for network and data symbol errors. Receive data [RXD] is clocked into a register using the 25 MHz recovered clock for 100Base-X or 2.5 MHz clock for 10Base-X. The Preamble and Start Frame delimiter (SFD) are scanned to locate the Destination address (DA) and the Source address (SA). An addressing mechanism uniquely identifies each MU9C8358L in a system. The Master MU9C8358L schedules communication with the host processor and the CAM through an arbitration process. Once the system is initialized and configured, highest-priority is given to network traffic. The LANCTL block generates the command cycles and operational codes to complete CPU-requested actions and network-generated requests. The CPU must initialize the CAM, write the permanent station list, and initiate other housekeeping functions. Network traffic initiates DA filtering, SA learning, and time stamp updates. All state-machines required for real-time operations are implemented in the ASIC hardware; the host CPU runs the non-time-critical initialization routine. Information on the LANCAM operation and instruction set can be found in the appropriate LANCAM data sheet for each device.
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08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 'HVWLQDWLRQ $GGUHVV 3UR.HVVLQJ Once configured, the MU9C8358L will extract the DA from the frames that are received through the MII ports. An automatic address processing function is subsequently triggered. Once the DA processing function is triggered, the frame is monitored to detect whether it is a broadcast, multicast, or unicast frame and the appropriate actions are taken. DA processing consists of the following actions: * * * Packets are characterized as Broadcast, Multicast, or Unicast types. Unicast packets initiate a search of the CAM for existing entries. If a DA match is found, the Port ID read from the CAM is compared to the Source Port ID. If the Source Port ID and Destination Port ID match, the frame is rejected. If the Port IDs are different, the Tag information is made available for MACs that support Tag switching, through the Tag port. If the MU9C8358L rejects the frame, it asserts the Reject output pin (REJ) and forces the MII RX_ER output (FRX_ER) HIGH for the appropriate MII Port. This causes the MAC to discard the frame. Once the DA processing function is complete, the MU9C8358L stores the result. This result indicates the characterization of the processed frame. (Broadcast, Multicast, or Unicast) and the Source Port ID. Additionally, if a unicast frame was processed, the result of the search and the port ID of the DA is also stored. Finally, the detail of whether the Destination port and the Source port are identical is also stored. The result of DA processing may be read in two ways. An interrupt may be sent to the host processor indicating that there is a result available. The host processor would read the result from an internal Result Data register. Alternatively, external circuitry can monitor the status of the Result Port Data valid (RP_DV) output pin. This output indicates that there is a result available in the internal register, which can be read through the Result port. The external circuitry can read the data by asserting the Result Port Select (RP_SEL) pin. Assertion of Result Port Next (RP_NXT) clears the value and advances the next entry if there is one available.
)XQ.WLRQDO 'HV.ULSWLRQ 6RXU.H $GGUHVV 3UR.HVVLQJ Once configured, the MU9C8358L also will perform SA processing functions after the address information has been extracted from a received frame. The SA of each arriving frame is stored by the MU9C8358L for further processing, along with the ID of the port on which it arrived, and the current time stamp. Note that at start-up, permanent addresses and Port IDs are loaded into the LANCAM through the CPU port; as message traffic proceeds, new addresses are learned and added to the LANCAM database, and aged addresses are purged. SA processing consists of the following actions: The SA field is collected and temporarily stored. Note the SA cannot be a Broadcast or Multicast address by definition. * When the complete packet has arrived, the CRC field is checked and the length of the packet is checked (if the CRC facility is enabled and the packet is 10 Base - X). Any errors result in no further SA processing. * If the packet did not contain any errors (or the CRC check facility is disabled), the SA field is compared with the address fields that are stored in the LANCAM. * If a match is found, the Port ID and time stamp for that entry are updated. If no match is found, the SA is added to the CAM, along with the current time stamp and the Port ID assigned to that particular Source port. See the PCFG registers section for more information on the CRC check facility. *
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)XQ.WLRQDO 'HV.ULSWLRQ 0$& $GGUHVV 6WRUDJH When the MU9C8358L performs an SA processing function, it automatically extracts the MAC address from the packet. The database is searched and the MAC address is added to the LANCAM database if necessary. Similarly, when a DA processing function is performed, the MU9C8358L automatically searches the database for the extracted DA MAC address. It is important that the user is aware of the byte ordering of the 48-bit MAC address when it is stored in the LANCAM database. This is because the user must byte-order MAC addresses identically when a database entry is to be manually added or deleted. Similarly, if the user wishes to read out a MAC address, they also should be aware of the byte ordering when the relevant data registers are read. Throughout this data sheet MAC addresses are shown as bit 47 being the most significant bit, which is placed on the left. Similarly, bit 0 is shown as the least significant bit and placed on the right. Using this notation, the Individual/Group (I/G) bit subfield would be shown as bit 40. This bit would be the first bit of an address transmitted onto the serial network and also the first bit received. The IEEE 802.3 refers to the I/G bit subfield as bit 0. If the bit is set to 1, it indicates that the address is a group address. Conversely, if the bit is set to 0, it indicates it is an individual address. Figure 5 shows a typical 48-bit MAC address used in Ethernet or IEEE 802.3 networks.
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If the MAC address shown in Figure 5 is added to the database by the MU9C8358L, it is stored as follows: * * * * Segment 3 = 6002h Segment 2 = 128Ch Segment 1 = 5634h Segment 0 = Associated data (permanent bit, time stamp and port ID)
If the user wishes to use the built-in routines to manually add, delete, or read MAC addresses from the database, the System CAM Word registers (SCDW) are used as shown in Figure 6. It shows how the MAC address, used as an example in Figure 5, would be transferred using the SCDW registers. If the user intended to delete the MAC address, the SCDW registers would be written as shown in item 1 and the SDO_DELETE routine would be invoked. If the user intended to add the address manually, the SCDW registers would be written as shown in item 2 and the SDO_ADD routine would be invoked. Finally, if the user intended to read an entry, the SDO_READ routine would be invoked and the address would be read from the SCDW registers as shown in item 3. The built-in routines are explained more fully later in this document.
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)XQ.WLRQDO 'HV.ULSWLRQ ),)2 DQG 5HVXOW 3RUW When the DA sequence is executed, the result is stored in a FIFO for later collection by either the CPU over the Processor Bus from the Result register, or by external hardware attached to the Result port. ,QLWLDOL]DWLRQ At power-up or after a hardware reset, the host processor should download the LANCAM configuration and register contents to enable the LANCAM to operate as required. The LANCAM initialization and configuration that is downloaded by the CPU should do the following: The individual Page Address registers of each LANCAM in the LANCAM chain should be set with appropriate values. The Foreground Register set should be set to allow normal DA and SA filtering. This involves setting the Control, Segment Control, and Mask registers to suit. The Background Register set should be set to allow the background management tasks to be preformed. This involves setting the Control, Segment Control, and Mask registers to suit. The LANCAM should be configured to store 48-bit MAC addresses in segments 3-1 and the associated data in segment 0. The allocation of bits in the 16-bit associated data segment is specified in the description of the SCDW0 Association Data register. A full description of the configuration routine required for a typical eight port switch is given in AN-N24: Using the MU9C8358L Quad 10/100 Mb Ethernet Filter Interface in Switch Applications. 3HUPDQHQW 6WDWLRQ $GGUHVV Using the Add Entry routine, the nonvolatile station list can be added to the LANCAM by the host processor. The Associated Data bit 15 is set to 1, to indicate a permanent entry. Permanent entries are removed only with the Delete Entry routine. 0DQDJHPHQW The Delete Entry and Read Entry routines are available for database maintenance and housekeeping. Although permanent addresses cannot be purged, they can be deleted using the management Delete Entry routine. $JLQJ DQG 3XUJLQJ Time stamps are added automatically to the LANCAM entries by the MU9C8358L. Two counters are provided to store the current and purge time stamps. The Current Time Stamp is the 8-bit value that automatically is added or updated when a SA processing function is completed. The Purge Time stamp is the 8-bit value that is compared with the 8-bit time stamps stored with the LANCAM entries during purges. The initial value of the counters are STPURG = 01H and STCURR = 00H. The counters may be incremented individually through the CPU commands.
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The MU9C8358L building blocks are shown in Figure 4, and their functions are described by the following. 0,, ,QWHUID.H 0,, 3RUWV $ WKURXJK ' The incoming asynchronous receive data is registered for subsequent processing. MU9C8358L internal processing is synchronous with the system clock. 7DJ 3RUW ,QWHUID.H 7DJ 3RUWV $ WKURXJK ' Rejection of a packet is indicated by the assertion of REJ. The FRX_ER line, which otherwise reflects the state of the RX_ER pin, is forced to HIGH at the same time. If the DA is matched in the LANCAM, the TP_DV pin is asserted and the destination port ID, high-order bit first, is clocked out through the TP_SD pin transitioning after the RX_CLK rising edge. 0$& This block performs tasks that are a subset of the Ethernet MACs. It detects errors, (CRS, COL, RX_ER, and Runt Frame), determines the start of frame, parses addresses, computes the CRC for 10Base-X packets, and formats the 4-bit nibbles into 48-bit SA and DA registers. $UELWHU The arbiter performs prioritization of internal functions and resource allocation. The arbiter allows two MU9C8358Ls to be cascaded and to share a single CAM database. The arbitration scheme requires that one MU9C8358L be the master and the other be the slave. Setting the bits 2-0 in the CHIPROL register to 000 identifies the Master. The MU9C8358L will function either as a Master or a Slave, and arbitration is transparent to the user. /$1&$0 6HTXHQ.HU /$1&7/ The sequencer is a state machine that generates the control signals required for CAM read and write cycles, and multiplexes appropriate data and operational codes to LANCAM data lines. The sequencer operations are: * * * * * * * Execute LANCAM cycles for CPU port DA processing SA processing Purging of aged entries Add Permanent Entries to LANCAM database Delete Entries from LANCAM database Read Entries from the LANCAM database.
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)XQ.WLRQDO 'HV.ULSWLRQ Either the CPU or the external INCR pin can increment both counters simultaneously. Whenever STPURG is incremented, a purge operation is initiated. The counters roll-over so the times should be thought of as slots to be used and reused in a round-robin fashion. The existence of two counters (time stamps) allows the data-aging rate to be varied according to network traffic density. When the difference between the counters is large (default), the address data is purged less frequently; shrinking the counter difference causes the data to age sooner. Incoming SAs are time stamped or updated with the current value of STCURR. Older entries time stamped with the same value as STPURG are purged upon the increment of STPURG. The permanent address database built using the Add routine is not affected by time stamps. The data age gap is effectively the length of time an entry will exist in the LANCAM database if it is not updated. This gap is the difference between the STCURR and STPURG counter. When network traffic is low, STCURR may be increased in order to increase the length of time an entry will exist. When network traffic is high, STPURG may be increased in order to decrease the length of time an entry will exist. When STPURG is incremented older entries are also purged from the database if their time stamp matches STPURG. STCURR and STPURG may be incremented simultaneously to keep the data age gap constant and to purge the older entries from the database. To maintain "current" time, STCURR is advanced in any one of the three ways: 1. The CPU issues an increment STCURR command. Only the STCURR counter is increased. 2. The CPU issues an increment STCURR and STPURG command. Both counters are increased simultaneously. 3. The INCR pin is asserted. Both counters are increased simultaneously. To maintain "purge" time and to purge aged CAM entries, STPURG is advanced in any one of the three ways: 1. The CPU issues an increment STPURG command. Only the STPURG counter is increased. 2. The CPU issues an increment STCURR and STPURG command. Both counters are increased simultaneously. 3. The INCR pin is asserted. Both counters are increased simultaneously. If the STPURG value was incremented, the MU9C8358L initiates a purge operation using the new STPURG value. STPURG should never be incremented to equal STCURR.
08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H The time stamping of LANCAM entries and the procedure required to initiate a purge is explained as follows: 1. Incoming SAs to be learned are associated with the most recent STCURR value. The time stamps of each SA already in the CAM database is updated to STCURR, each time a packet with that SA is processed. 2. STPURG and STCURR are advanced as described earlier to purge entries that have the same time stamp value as STCURR. $JLQJ DQG 3XUJLQJ ([DPSOH This example begins with the initial defaults, STCURR = 00H and STPURG = 01H. As packets arrive, learned or refreshed, SAs are labeled with STCURR = 00H. (At that moment STPURG = 01H). Increment, either hardware or software initiated, results in STCURR = 01H and STPURG=02H. A purge operation is initiated that eliminates all CAM entries with time stamp = 02H. The oldest entries (SAs) that have not been updated in 255 increment times are purged automatically without further involvement. If the CAM Full flag is asserted, an interrupt (if configured) to the CPU is generated. Assume that STCURR = F0H, and STPURG = F1H. The CPU may initiate an increment STPURG operation so that older entries may be purged. This increases the value of STPURG to F2H. A purge operation is initiated that will eliminate all CAM entries with time stamp = F2H. The CPU should monitor the System Status register, and if the CAM is still full, the operation can be repeated until entries are purged and the CAM Full flag is de-asserted. Assume that STPURG was incremented 128 times. This would purge the oldest half of the time stamp values and thus, reduce the maximum age to half the previous 255. This is accomplished without changing STCURR. &5& DQG 2WKHU 'DWD ,QWHJULW\ &KH.NV For 10Base-X packets, a 32-bit cyclic redundancy check is calculated from the data frame (exclusive of the preamble and start frame delimiter) and compared to the frame check sequence (FCS). This check is only performed if the PCFG register for the appropriate port is set accordingly to enable the facility. Also, according to the MII interface specifications, the RX_ER, CRS, and COL signals are monitored and error conditions are recognized. If any error is identified, the source address is not processed. This is intended to maintain the integrity of the LANCAM database.
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One set of registers is available to address up to two MU9C8358L components and their attached LANCAMs as a single system. The application decodes one range of addresses to produce a Processor Chip Select System 7DEOH 6\VWHP 5HJLVWHUV
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signal (/PCSS) that is shared among all MU9C8358L components. The lowest address in this application-defined address range, shown in Table 3, is referred to as SYSTEM_BASE.
6\VWHP 6WDWXV 5HJLVWHU The System Status register (SSTAT) provides a CPU visibility into the state of the LANCAM array. The /FF bit indicates the current state of the Full Flag output of the LANCAM array. The /MF bit indicates the Match Flag output of the LANCAM array.
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attached. A 50 MHz clock is assumed. The INV_REJ bit configures all REJ ports A through D to be active LOW instead of active HIGH.
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6\VWHP 6WDWL. &RQILJXUDWLRQ 5HJLVWHU The System Static Configuration register (SSTAT) allows the CPU to configure the LANCAM array. These are set and forget values. The CAM_SPD sets the controller to match the speed grade of the LANCAM components
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6RIWZDUH 0RGHO 6\VWHP '\QDPL. &RQILJXUDWLRQ 5HJLVWHU The System Dynamic Configuration Register (SDCFG) allows the CPU to control the MU9C8358L /RESET_LC output pin. This pin normally would be connected to the /RESET input of all the LANCAMs in a chain of LANCAMs. When the RST_CAM bit is logic 0 the /RESET_LC output is LOW and when the RST_CAM bit is logic 1 the /RESET_LC output is HIGH. Note that if a hardware reset is performed by taking the MU9C8358L /RESET input LOW, /RESET_LC is asserted LOW. However, once /RESET has been taken HIGH, /RESET_LC remains LOW, holding the LANCAM(s) in the reset condition. The RST_CAM bit must be set to 1 to return /RESET_LC HIGH and hence allow the LANCAMs to operate normally.
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08&/ 4XDG 0E (WKHUQHW )LOWHU ,QWHUID.H 6\VWHP &$0 :RUG 5HJLVWHUV When using the series of built-in routines, the SCDW registers are used to transfer data. The bit mapping is different for each routine. Please refer to the appropriate mapping for the relevant routine. Also refer to the MAC Address Storage section on page 11.
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During the LANCAM initialization and configuration process, SCDW0 is used with SLCCS to configure the LANCAMs. When SCDW0 is used to transfer associated data, the bit mapping is as shown.
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6\VWHP 7DUJHW 5HJLVWHU The System Target Register (STARG) allows the CPU to determine how events are to be handled. The INCR_PIN bits enable or disable to INCR hardware input. The EN_FF_INT bits enable or disable whether the LANCAM /FF output produces an interrupt when the LANCAM is full.
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6\VWHP 7LPH 6WDPS 3XUJH 5HJLVWHU The System Time Stamp Purge register (STPURG) stores the purge time stamp value. It is a read-only register, but it may be incremented by writing an arbitrary value to the SDO_INCPR register.
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6\VWHP 7LPH 6WDPS &XUUHQW 5HJLVWHU The System Time Stamp Current register (STCURR) stores the current time stamp value. It is a read-only register, but it may be incremented by writing an arbitrary value to the SDO_INCTS register.
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6RIWZDUH 0RGHO When the host CPU wishes to write to the LANCAM (at initialization) bit 4 is set to one while setting bits 3-0 to the values required for a LANCAM data or command cycle. The data or command to be transferred to the LANCAM should be loaded into the SCDW0 register prior to the cycle being initiated. Each LANCAM cycle is a four step process and is described as follows: 1. Load SCDW0 with 16-bit data or command. 2. Load SLCCS with cycle value to take /E HIGH. 3. Load SLCCS with cycle value to take /E LOW. 4. Load SLCCS with cycle value to take /E HIGH. For example a TCO CT command cycle would be SCDW0 = 0200H, SLCCS = 19H, 11H, 19H.
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6\VWHP 6WDWXV :RUG 5HJLVWHUV The Status Word registers store the 32-bit LANCAM status register value after the LANCAM entry read routine is performed. * * SCSWA stores the lower 16 bits of the status register SCSWB stores the upper 16 bits.
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6\VWHP 6$ 2S&RGH 5HJLVWHUV The SA Op-Code registers store the LANCAM Op-Code values required when the MU9C8358L performs the automatic SA search routine. * * SSAU stores the code required to update an SA SSAL stores the code required to learn an SA.
These registers have the default values required to perform the routines described in Built-in Routines.
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6\VWHP &RPPDQG 5HJLVWHUV The System Command registers allow the CPU to execute transactions applied to a LANCAM array. There are seven command registers and they have the prefix SDO. Each register is used to initiate a built-in routine that allows general LANCAM housekeeping tasks to be performed. The housekeeping sequence is initiated by writing any arbitrary value to the appropriate register. Descriptions of the routines performed when SDO_ADD, SDO_DELETE, SDO_READ, and SDO_SETADD are accessed as shown in Built-in Routines. SDO_INCTS, SDO_INCPR, and SDO_INCTSPR control the time stamp counters. SDO_INCPR and SDO_INCTSPR also cause the purge routine described in Built-in Routines to be initiated. The MU9C8358L may hold PROC_RDY inactive if it is processing any high-priority DA and SA searches. The registers and their address values are found in Table 3.
6\VWHP /$1&$0 &RQWURO 5HJLVWHU The System LANCAM Control register enables the host CPU to initialize and configure the LANCAMs. During normal system operation bit 4 should be set to zero to disable the LANCAM control bits.
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The system should decode one unique range of addresses to produce an individual chip select (/PCS) signal for each MU9C8358L component. The lowest address in this application-defined address range is referred to as CHIP_BASE. One set of these registers is available for each MU9C8358L in a system. Table 20 shows the Chip registers and their address values. &KLS 5ROH 5HJLVWHU The Chip Role register stores the designation of each MU9C8358L. When two MU9C8358Ls are chained together the device that is hardware configured as the MASTER device must have this register loaded with 000H. The other MU9C8358L must be designated as the SLAVE and be loaded with any other value other than 000H. When only one MU9C8358L is used it must be designated as MASTER.
Note: Any access to the System registers using /PCSS are ignored until this register is properly set. This occurs because the CHIPROL register always defaults to a SLAVE designation. Therefore, the system software MUST configure the CHIPROL register(s) before any System register accesses are made. 7DEOH &+,352/ &KLS 5ROH 5HJLVWHU 0DSSLQJ
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5HVXOW 6WDWXV 5HJLVWHU The Result Status register is used to convey whether the Result Data register stores any valid result data. Reading this register resets the /INTR pin if it was asserted because of result data being processed (after all valid result data is read).
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5HVXOW 'DWD 5HJLVWHU The Result Data register stores the result of the automatic SA and DA processing.
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&KLS 9HUVLRQ 5HJLVWHU The Chip Version register stores the version of the chip. The value of this read-only register will be incremented for each subsequent release. 7DEOH &KLS 5HJLVWHUV
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6RIWZDUH 0RGHO 3RUW &RQILJXUH 5HJLVWHU The Port Configure register (A through D) enables or disables the 10Base - X CRC check facility. If the facility is enabled, 10Base - X packets found to have CRC errors will not have their Source address processed. If the facility is disabled, the Source address of 10Base - X packets are processed regardless of CRC errors, assuming the PTARG register is configured appropriately. This register only enables a CRC check for 10Base - X packets. The facility should be disabled (bit 1=0) for 100Base - X packets.
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Each MU9C8358L supports four ports. Those ports are addressed as an offset to the CHIP_BASE for the MU9C8358L in which they are implemented. Table 23 shows the Port registers and their address values. 3RUW ,' 5HJLVWHU The Port ID register (A through D) stores the ID associated with each of the four ports in a MU9C8358L. The 6-bit value is the value added to LANCAM entries when the SA search routine is performed. It is important to note that when two devices are used to provide support for eight ports, the eight Port_ID registers are given different values.
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6RIWZDUH 0RGHO 3RUW 7DUJHW 5HJLVWHU The Port Target registers (A through D) allow the operating conditions of each port to be set. Bits 3-0 are reserved and should be set to 0H. Bits 5-4 determine what action is taken after the DA is extracted from a frame that
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was received on the appropriate MII port. Bits 7-6 determine what action is taken after the SA is extracted from a frame that was received on the appropriate MII port.
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6RIWZDUH 0RGHO 2. Write the associated data for this entry into SCDW0. The port ID should be set in bits 13-8 and bit 15 should be set HIGH if the entry is to be permanent. 3. Initiate the add sequence by writing any value to the SDO_ADD register. ,QLWLDWH 6HW $GGUHVV 6HTXHQ.H 1. Write the desired address of the CAM entry to be read into SCDW0. 2. Initiate the set address sequence by writing any value to the SDO_SETADD register.
Note: This sequence should be initiated prior to the read entry sequence being initiated in order to specify the address that should be read.
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The MU9C8358L contains seven built-in routines that can be invoked or triggered by writing any arbitrary value to the appropriate System Command register. * * Five built-in routines that perform general system management functions. Two routines that alter the data-age gap between the two time stamp counters.
Details of the built-in routines that are performed when invoked can be found in Applications: Built-In Routines. Details of the appropriate register for each routine can be found in Operational Characteristics: Software Model-System Registers. Each of the seven routines is explained below. ,Q.UHPHQW WKH &XUUHQW 7LPH 6WDPS Initiate the STCURR increment sequence by writing any arbitrary value to SDO_INCTS. ,Q.UHPHQW WKH 3XUJH 7LPH 6WDPS Initiate the STPURG increment sequence by writing any arbitrary value to SDO_INCPR. ,Q.UHPHQW WKH &XUUHQW 7LPH 6WDPS DQG 3XUJH 7LPH 6WDPS Initiate the STCURR and STPURG increment sequence by writing any arbitrary value to SDO_INCTSPR. ,QLWLDWH 'HOHWH 6HTXHQ.H 1. Write the address to be deleted into System Command Data Word (SCDW) 2, 1, and 0. Bits 47-32 should be written into SCDW 2, bits 31-16 into SCDW1, and bits 15-0 into SCDW0. 2. Initiate the delete sequence by writing any value to the SDO_DELETE register. ,QLWLDWH $GG 6HTXHQ.H 1. Write the address to be added into System Command Data Word (SCDW) 3, 2, and 1. Bits 47-32 should be written into SCDW 3, bits 31-16 into SCDW2, and bits 15-0 into SCDW1.
,QLWLDWH 5HDG (QWU\ 6HTXHQ.H 1. Write the Page Address to the CAM device to be read into SCDW0. This should match the value that was configured during any CAM configuration routine. 2. Initiate the read entry sequence by writing any value to the SDO_READ register. 3. The specified entry can be read from SCDW3, 2, and 1 and the associated data can be read from SCDW0. Bits 47-32 should be read from SCDW 3, bits 31-16 from SCDW2, and bits 15-0 from SCDW1. 4. The CAM Status Register bits 31-16 associated with the entry can be read from the System CAM Status Word B (SCSWB) register. 5. The CAM Status Register bits 15-0 associated with the entry can be read from the System CAM Status Word A (SCSWA) register.
Note: This sequence should be initiated in conjunction with the set address sequence in order to specify the address that should be read. If successive entries are to be read, SDO_SETADD is used only once as the CAM Address register will increment automatically.
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&DV.DGLQJ 7ZR 08&/ &RPSRQHQWV Two MU9C8358L devices may be connected together to support eight 10/100Mb ports. When this is done, one device is hardwired as the Master and the other is hardwired as the Slave. The Master device supplies the RESET_LC output to the LANCAM device(s). Each MU9C8358L has its own /PCS input to allow the host processor to configure its Chip and Port registers. Figure 7 shows the required connections for cascading two devices. Both devices share the same /PCSS input that allows the system registers to be configured. When the host processor is accessing the system registers, the Master responds to all the commands, whereas the Slave only responds to a subset of the commands. For example, only the Master device will configure the LANCAM database and run management routines. The Slave device needs to respond to configuration register writes and reads, time stamp register writes and increments, and Result register reads.
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When LANCAMs are cascaded in this way, the system Full and Match flags are connected to the MU9C8358L /FI and /MI inputs respectively. Please refer to the LANCAM B Family data sheet for a comprehensive description of the device.
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The MU9C8358L contains built-in LANCAM routines that perform all the necessary LANCAM operations. The DA and SA search routines are performed automatically by the device in order to provide the search result and Definitions: aaaaH = CAM Address value (Hexadecimal) ddddH = Data value (Hexadecimal) ppppH = CAM Page Address value (Hexadecimal) xxxxH = "Don't Care" 'HVWLQDWLRQ $GGUHVV 6HDU.K 5RXWLQH
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Notes:
1. 2. 3. 4. 5. 6. The MU9C8358L LANCAM interface must be configured to accept the speed grade of the LANCAM being used. Once it is configured for the appropriate speed grade (70 ns, 90 ns, or 120 ns) the cycle time will vary accordingly. The MU9C8358L contains built-in routines that include LANCAM short, medium, or long cycles. The cycle will vary depending upon what LANCAM cycle is being performed by the MU9C8358L. A LANCAM read cycle initiated by the MU9C8358L could be to the internal memory array or to the LANCAM registers. The timing specified meets the requirements to successfully read from either source. CAM Control signals are /CM, /W, and /EC. The /FI input is latched by the MU9C8358L on every rising edge of SYSCLK. The LANCAM interface is designed to work properly with up to four LANCAMs.
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Figure 13: Timing Diagram for LANCAM Interface - Read
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Figure 14: Timing Diagram for LANCAM - Write
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Figure 15: Timing Diagram for LANCAM Interface - Compare
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